This invention relates to surface planarization technology. More specifically, it relates to electropolishing technology for planarizing surfaces having low aspect ratio recesses or trenches.
In the fabrication of integrated circuits, as the number of levels in an interconnect technology is increased, the stacking of additional layers on top of one another produces a more and more rugged topography. Without planarization, the microscopic canyons that result on the integrated circuit surface from stacking of device features create a topography that would eventually lead to defects in the integrated circuit that would make the circuit unusable.
One method of planarization used in the art is chemical mechanical polishing (CMP). CMP is a process that uses a mixture of abrasives and pads to polish the surface of the integrated circuit. Unfortunately, CMP polishing techniques are difficult to control; the end-point can be difficult to detect. They are also expensive. The high equipment and waste handling cost and low throughput contribute the overall expense of CMP.
Another method of planarization involves an electrolytic technique such as electropolishing. Electropolishing is a low cost alternative technique to CMP. Lower capital cost, easier waste handling, and much higher processing rates make it a desirable alternative to CMP. Electropolishing is a method of polishing metal surfaces by applying an electric current through an electrolytic bath, as described for example in McGraw-Hill Encyclopedia of Science & Technology, pp. 810-811, 1982. The process may be viewed as the reverse of electroplating. Various patents describe such electropolishing techniques.
U.S. Pat. No. 5,096,550 to Mayer et al. ('550 patent), describes a method and apparatus for the removal of metal in the formation of planarized interconnects for integrated circuits. The Mayer et al. patent is incorporated herein by reference for all purposes. The Mayer et al. method and apparatus employ an electro-removal technique, including generally electrochemical etching and particularly electropolishing. A primary object of the '550 patent is to provide a spatially uniform polishing, etching or removal rate by controlling both the edge effects and the larger spatial non-uniformities. A second object of the '550 patent is to polish the surface, that is, to reduce surface roughness at the same time as etching it. A third object of the '550 patent is to remove material from the surface rapidly.
U.S. Pat. No. 3,849,270 to Takagi et al. describes a process of manufacturing semiconductor devices using electrolytic etching to remove a coating layer from an insulating layer.
U.S. Pat. No. 5,256,565 to Bernhardt et al. for electrochemical planarization describes a method and apparatus for forming a thin film planarized metal interconnect which is flush with the surrounding dielectric layer. In one described embodiment, a planarized metal layer is formed by controlled deposition, using an isotropic or other self-planarization process, of a layer having a depth at least about half the width of the widest feature to be filled in the dielectric layer. The metal layer is then etched back by electropolishing.
A problem arises during the electropolishing of surfaces in which a large number of low aspect ratio (larger width than depth) features exist. Trenches cut in a dielectric layer (for a damascene process) to define contact pads often have low aspect ratios. Conformal metalization processes typically do not "close" such features because to do so would require depositing a very thick metal layer, which would be uneconomical to add and later remove. Conventional electropolishing techniques can planarize a surface in which the feature to be planarized is no more than perhaps three times as wide as it is deep. For features wider than these, the rate of removal is essentially uniform everywhere, making electropolishing planarization very difficult, if not impossible.
Electroplating is one conformal deposition process. Because electroplating is highly isotropic, it can be shown both theoretically and experimentally that high aspect ratio features (i.e. depth to width&gt;3:1) are rapidly filled, and the metal above them becomes rapidly planarized (due to the fact that film growth is not directionally dependent). Therefore, electroplating is a preferred method of metalization. Typically a metalization thickness of 1/2 the feature width is needed to close the cleft over the feature. Further addition of metal reduces the size of the cleft above the feature. Surfaces in which sufficient metal to fill and produce small clefts above high aspect ratio features will fill low aspect ratio features, but the latter features exhibit large recesses in the filled profile equal to the original feature depth (see FIG. 3) which are very difficult to planarize using conventional electropolishing technology. Today, features that vary in size by two orders of magnitude are typical. A 1 .mu.m deep feature can have widths of from 0.2 .mu.m to 100 .mu.m. The current invention enables materials and methods for accomplishing planarization of damascene filled surfaces of a large range of feature sizes.
The current state of electropolishing technology has additional difficulties. For example, electropolishing typically requires highly viscous electrolyte baths (e.g., 85% phosphoric acid (H.sub.3 PO.sub.4) in water, or with some added ethylene glycol). While these baths are effective in achieving good polishing and planarization rates, they make it difficult to remove defect-causing bubbles and to handle the fluids in general. Note that a hydrogen generating reaction may take place at the cathode. The hydrogen can become entrained in the electrolyte, complicating tool design and presenting a potential safety hazard. In addition, these baths also have high resistivities, making for large power requirements and substantial amounts of generated heat (which must be removed to maintain a constant process control).
What is needed therefore is improved electropolishing technology for planarizing conductive layers on integrated circuits and other substrates.